1. Technical Field
The embodiments described herein relate to a semiconductor memory device and, more particularly, to a semiconductor memory device including a row decoder that controls the operation of mats and word lines of the mats.
2. Related Art
Generally, a conventional semiconductor memory device includes a plurality of banks. Each bank includes a plurality of mats and each mat has a plurality of memory cells.
As is well known, a memory cell in a conventional device includes word lines, bit lines crossing the word lines, switching devices formed at points at which the word lines cross the bit lines, and capacitors in which information of the bit lines is selectively stored by the switching devices.
Referring to FIG. 1, a semiconductor memory device, for example, includes four banks BANKs 10a to 10d. In FIG. 1, an x-axis denotes the extending direction of word lines constituting the banks and a y-axis denotes the extending direction of bit lines constituting the banks. Each of the banks 10a to 10d includes a plurality of mats 15a. The mats 15a are arranged in the form of a matrix in the banks 10a to 10d. In FIG. 1, reference numeral 15L denotes groups of mats arranged in the same row, i.e. a mat row.
Generally, row decoder groups 20a and 20b and a fuse unit 30a are disposed between the banks 10a and 10b in the x-axis direction, and row decoder groups 20c and 20d and a fuse unit 30b are disposed between the banks 10a and 10b in the x-axis direction. Each of the row decoder groups 20a to 20d includes a plurality of row decoders 21 disposed corresponding to the mat rows 15L.
As is also well known, each row decoder 21 may include a normal word line buffer unit (not shown), a sense amp selector (not shown), a redundancy word line driving controller (not shown), a row decoder controller 21a, a word line driving unit (not shown), a sense amp driving unit (not shown) and a redundancy word line driving unit (not shown). Among them, the row decoder controller 21a makes up the largest portion of the unit row decoder 21.
The fuse unit 30a includes redundancy cells or fuses (not shown) for correcting a defective word line of the banks 10a and 10b, and the fuse unit 30b includes redundancy cells or fuses (not shown) for correcting a defective word line of the banks 10c and 10d. 
Meanwhile, a peripheral area 40 is disposed between the banks 10a and 10c arranged in the y-axis direction and between the banks 10b and 10d arranged in the y-axis direction. In the peripheral area 40, a plurality of pads 41 are disposed in portions corresponding to the banks 10a to 10d, and row address latch decoder blocks 42 that provide latched row address signals are disposed in portions corresponding to the row decoder groups 20a to 20d. 
Conventional semiconductor memory devices are incorporating an increasing amount of devices, while still being required to provide high speed operation. Thus, a technology capable of integrating many mats in a limited bank is desirable.
As described above, since the unit row decoders 21 must correspond to the mat rows 15L, as the number of the mats is increased, the number and area of the unit row decoders 21 must also be increased.
However, it is difficult to increase the area of the unit row decoders 21 because the intervals among the banks 10a to 10d are limited.